With increasing demands for advanced device structures, the use of dopants to control the conducting channel in traditional CMOS devices is reaching its limits. As CMOS devices are scaled to the nanometer regime, SOI structures including fully depleted (FD) and partially depleted (PD) structures have provided an evolutionary pathway for MOSFETS operating at low power. CMOS designs below about 0.1 microns are plagued by shortcomings such as short channel effects (SCE) and gate oxide tunneling. In addition, severe restraints are placed on the uniformity of the active silicon channel region which is correspondingly reduced in dimension. One approach to overcome such shortcomings is to change the device structure such that the gate length may be scaled down while using thicker gate oxides and increased active silicon channel dimensions.
For example FET designs have included forming non-planar active silicon regions by forming double gated fin-like silicon channel structures also referred to as finFETs and triple gated structures referred to a tri-gate FETs.
While these structures have been shown to have acceptable short channel behavior and may be formed with conventional gate oxide thicknesses to overcome gate oxide tunneling, majority carrier mobility, is frequently compromised by prior art SOI formation processes.
Another shortcoming of prior art SOI fabrication processes and devices is that the potential for damage from ESD events is increased due to the relatively thin silicon regions formed over the buried oxide layer. For example Input/output (I/O) areas are typically electrically connected to the upper silicon channel layer, which in SOI devices is not sufficiently thick to adequately dissipate excess heat generated by ESD events thereby potentially causing catastrophic failure of the device.
There is therefore a need in the microelectronic integrated circuit (IC) processing art to develop a method for forming active silicon channel regions including non-planar structures such as those included in finFETs and tri-gate FETs to improve charge carrier mobility as well as improving ESD protection for SOI circuits.
It is therefore an object of the invention to provide a method for forming active silicon channel regions including non-planar structures such as those included in finFETs and tri-gate FETs to improve charge carrier mobility as well as improving ESD protection for SOI circuits, while overcoming other shortcomings and deficiencies of the prior art.